1. Field of the Invention
The present invention relates generally to a method for fabricating semiconductor devices. More specifically, a two-stage method for making buried strap out-diffusions of a vertical transistor is disclosed for reducing or avoiding potential buried strap out diffusion leakage.
2. Description of the Prior Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size, which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device. For example, dynamic random access memory devices (DRAMs), which use vertical metal oxide semiconductor field effect transistors (MOSFETs) with deep trench (DT) storage capacitors, have a minimum features size of approximately 0.1. m xcx9c0.15. m. Below that size, the internal electric fields exceed the upper limit for storage node leakage, which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.
Please refer to FIG. 1 to FIG. 7. FIG. 1 to FIG. 7 are schematic diagrams illustrating a method for making a vertical transistor of a deep-trench DRAM unit according to the prior art. As shown in FIG. 1, a deep trench structure 11 is provided in the semiconductor substrate 10. To form the deep capacitor structure 11, a conventional dry etching method such as a reactive ion etching (RIE) is used to etch the semiconductor substrate 10 with a patterned pad layer 14 as an etching mask. A layer of N type doped first polysilicon is deposited at the bottom of the deep trench structure 11, which functions as a storage node of the deep-trench DRAM unit. As shown in FIG. 2, a conformal layer of silicon oxide (not shown) is deposited on the inner surfaces of the deep trench structure 11 and over the pad layer 14. An anisotropic etching process is then carried out to remove the silicon oxide layer laid on top of the pad layer 14 and the silicon oxide layer at the bottom of the deep trench structure 11, leaving the silicon oxide layer on sidewalls 13 of the deep trench structure 11, as indicated by numeral 16, which is hereinafter referred to as a collar oxide layer 16. As shown in FIG. 3, a layer of N type doped second polysilicon 22 is deposited over the first polysilicon. 12 at the bottom of the deep trench structure 11. As shown in FIG. 4, the collar oxide layer 16 on the sidewalls 13 of the deep trench structure 11 is selectively etched to form collar oxide layer 16xe2x80x2.
As shown in FIG. 5, a layer of non-doped third polysilicon 32 is deposited over the second polysilicon layer 22. The third polysilicon 32 is used as a diffusion path for dopants in the second polysilicon layer 22. Through the third polysilicon 32, the dopants such as arsenic or phosphorus out-diffuse to the neighboring substrate body in the subsequent thermal processes.
As shown in FIG. 6, a high-density plasma chemical vapor deposition (HDP CVD) is carried out to deposit a HDP oxide layer (not shown) at the bottom, sidewalls 13 of the deep trench structure 11, and on the top of the pad layer 14. The HDP oxide layer on the sidewalls 13 of the deep trench structure 11 is much thinner than the HDP oxide layer at the bottom of the deep trench structure 11. Thereafter, an isotropic dry etching is performed to remove the thin HDP oxide layer on the sidewalls 13 of the deep trench structure 11, leaving a thickness of the HDP oxide layer at the bottom of the deep trench structure 11. The remaining HDP oxide layer atop the third polysilicon layer 32 at the bottom of the deep trench structure 11 is denoted and referred to as a Trench Top Oxide (TTO) layer 42. For a deep-trench DRAM having a critical line width of 0.1 micron, the minimum thickness of the TTO layer 42 is about 300 angstroms. Below this limit, the isolation between the vertical transistor and the deep trench capacitor deteriorates.
As shown in FIG. 7, a thermal process is carried out to form a gate-insulating layer 54 on the exposed sidewalls 13 of the deep trench structure 11. During the thermal process, the dopants in the second polysilicon layer 22 out-diffuse to the substrate 10 through the third polysilicon layer 32, thereby forming a buried strap out-diffusion 52, which is used to electrically connect a drain of the vertical transistor with the underlying storage capacitor.
However, the above-mentioned prior art method has several drawbacks. As specifically indicated in FIG. 7, the buried strap out-diffusion 52 has a lateral diffusion length X and a longitudinal diffusion length Y that is substantially equal to the lateral diffusion length X. It is understood that the longitudinal diffusion length Y has to be slightly greater than the thickness of the TTO layer 42 only such that the buried strap out-diffusion 52 can electrically connect the vertical transistor with the deep trench capacitor. By way of example, in a case that the TTO layer 42 is 300-angstrom thick, the longitudinal diffusion length Y of the buried strap out-diffusion 52 is greater than 300 angstroms, say, 400 angstroms. Unfortunately, the lateral diffusion length X of the buried strap out-diffusion 52 will also exceed 300 angstroms. This leads to increased buried strap (BS) leakage because the short distance between two out-diffusions of two adjacent deep trench DRAM units.
Moreover, large lateral diffusion length X of the buried strap out-diffusion 52 also hinders the possibility of further miniaturizing the DRAM cell dimension. In addition, the non-uniformity of the TTO oxide layer 42 results in reliability and process control problems. When the thickness of the TTO oxide layer 42 varies, a longer thermal process is needed to ensure that sufficient longitudinal diffusion length Y of the buried strap out-diffusion 52 is accomplished, and longer thermal process means higher thermal budget and lower throughput.
Accordingly, it is a primary objective of this invention to provide an improved method for fabricating a vertical transistor to solve the above-mentioned problems.
It is a further objective of this invention to provide a two-stage method for fabricating buried strap out-diffusions of a vertical transistor, thereby reducing or eliminating potential buried strap (BS) leakage and shortening thermal budget.
Briefly summarized, the preferred embodiment of the present invention discloses a two-stage method for fabricating buried strap out-diffusions of vertical transistors. A substrate having a deep trench is provided. A first conductive layer is deposited at the bottom of the deep trench. A collar oxide is formed on sidewalls of the deep trench. A second conductive layer is deposited within the deep trench atop the first conductive layer. The collar oxide is then etched back to a predetermined depth. A third conductive layer is deposited directly on the second conductive layer. A trench top oxide (TTO) layer is formed on the third conductive layer. A spacer is formed on the sidewalls of the deep trench. A portion of the TTO layer is etched away to form a recess underneath the spacer, which exposing the substrate in the deep trench. Thereafter, a doping process is carried out to form a first diffusion region through the recess, followed by spacer stripping. Finally, a thermal process is performed to out-diffuse dopants of the second conductive layer to the substrate through the third conductive layer, thereby forming a second diffusion region that merges with the first diffusion region.
Other objects, advantages, and novel features of the claimed invention will become more clearly and readily apparent from the following detailed description when taken in conjunction with the accompanying drawings.